Index: arch/sparc64/include/cpuset.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/cpuset.h,v retrieving revision 1.2 diff -r1.2 cpuset.h 48,49c48 < #define CPUSET_ALL(set) ((set) = (cpuset_t)-1) < #define CPUSET_ALL_BUT(set, cpu) ((set) = ~CPUSET_SINGLE(cpu)) --- > #define CPUSET_EXCEPT(set, cpu) ((set) & ~CPUSET_SINGLE(cpu)) Index: arch/sparc64/include/db_machdep.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/db_machdep.h,v retrieving revision 1.16 diff -r1.16 db_machdep.h 141a142,144 > #define DB_MAX_WIDTH 160 > #define DB_MAX_LINE 40 > Index: arch/sparc64/include/param.h =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/include/param.h,v retrieving revision 1.32 diff -r1.32 param.h 296a297,298 > > #define __HAVE_MD_KTR 1 Index: arch/sparc64/sparc64/db_interface.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/db_interface.c,v retrieving revision 1.77 diff -r1.77 db_interface.c 39a40 > #include "opt_ktr.h" 105c106 < #ifdef notdef_yet --- > #ifdef not_used 287a289,292 > #ifdef KTR > extern int ktr_mask; > int saved_ktr_mask = ktr_mask; > #endif 288a294,296 > #ifdef KTR > ktr_mask = 0; > #endif 316a325 > fplwp = NULL; 379a389,392 > #ifdef KTR > ktr_mask = saved_ktr_mask; > #endif > 1148c1161 < db_printf("cpu%d: self 0x%08lx lwp 0x%08lx pcb 0x%08lx\n", --- > db_printf("cpu%d: self 0x%08lx lwp 0x%08lx pcb 0x%08lx idle 0x%08lx\n", 1150c1163,1164 < (u_long)ci->ci_curlwp, (u_long)ci->ci_cpcb); --- > (u_long)ci->ci_curlwp, (u_long)ci->ci_cpcb, > (u_long)ci->ci_idle_u); Index: arch/sparc64/sparc64/genassym.cf =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/genassym.cf,v retrieving revision 1.36 diff -r1.36 genassym.cf 79a80 > include "opt_ktr.h" 91a93 > include 303a306,323 > > # KTR constants and fields > define KTR_COMPILE KTR_COMPILE > define KTR_TRAP KTR_TRAP > define KTR_PROC KTR_PROC > define KTR_PMAP KTR_PMAP > define KTR_INTR KTR_INTR > define KTR_ENTRIES KTR_ENTRIES > define KTR_SIZEOF sizeof(struct ktr_entry) > define KTR_TIMESTAMP offsetof(struct ktr_entry, ktr_timestamp) > define KTR_CPU offsetof(struct ktr_entry, ktr_cpu) > define KTR_DESC offsetof(struct ktr_entry, ktr_desc) > define KTR_PARM1 offsetof(struct ktr_entry, ktr_parms[0]) > define KTR_PARM2 offsetof(struct ktr_entry, ktr_parms[1]) > define KTR_PARM3 offsetof(struct ktr_entry, ktr_parms[2]) > define KTR_PARM4 offsetof(struct ktr_entry, ktr_parms[3]) > define KTR_PARM5 offsetof(struct ktr_entry, ktr_parms[4]) > define KTR_PARM6 offsetof(struct ktr_entry, ktr_parms[5]) Index: arch/sparc64/sparc64/ipifuncs.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/ipifuncs.c,v retrieving revision 1.1 diff -r1.1 ipifuncs.c 38a39,40 > #include "opt_ktr.h" > 40a43 > #include 48c51 < #define IPI_TLB_SHOOTDOWN 0 --- > #define IPI_TLB_SHOOTDOWN 1 53c56 < #define SPARC64_IPI_RETRIES 100 --- > #define SPARC64_IPI_RETRIES 10000 109,110c112 < sparc64_ipi_halt(arg) < void *arg; --- > sparc64_ipi_halt(void *arg) 124,125c126 < sparc64_ipi_pause(arg) < void *arg; --- > sparc64_ipi_pause(void *arg) 169,171c170 < sparc64_multicast_ipi(cpuset, ipimask) < cpuset_t cpuset; < u_long ipimask; --- > sparc64_multicast_ipi(cpuset_t cpuset, u_long ipimask) 191,192c190 < sparc64_broadcast_ipi(ipimask) < u_long ipimask; --- > sparc64_broadcast_ipi(u_long ipimask) 194d191 < cpuset_t cpuset; 196,197c193 < CPUSET_ALL_BUT(cpuset, cpu_number()); < sparc64_multicast_ipi(cpuset, ipimask); --- > sparc64_multicast_ipi(CPUSET_EXCEPT(cpus_active, cpu_number()), ipimask); 199a196,197 > int ipi_num = 0; > int ipi_ignore = 0; 204,206c202 < sparc64_send_ipi(upaid, ipimask) < int upaid; < u_long ipimask; --- > sparc64_send_ipi(int upaid, u_long ipimask) 208c204 < int i; --- > int i, ik; 210a207,211 > if (ipi_ignore) > return; > > ipi_num++; > 212c213,216 < KASSERT((ldxa(0, ASR_IDSR) & IDSR_BUSY) == 0); --- > > if (ldxa(0, ASR_IDSR) & IDSR_BUSY) { > __asm __volatile("ta 1; nop"); > } 228a233,235 > CTR3(KTR_SMP, "send_ipi: num %p, func %p, upaid %d", > intr_number, intr_func, upaid); > 238a246 > #if 0 240a249,255 > #endif > for (ik = 0; ik < 1000000; ik++) { > if (ldxa(0, ASR_IDSR) & IDSR_BUSY) > continue; > else > break; > } 242a258,260 > if (ik == 1000000) > break; > 246a265 > #if 0 250a270,271 > #endif > __asm __volatile("ta 1; nop" : :); 256,259c277,278 < int < sparc64_ipi_wait(cpus_watchset, cpus_mask) < cpuset_t __volatile *cpus_watchset; < cpuset_t cpus_mask; --- > static int > sparc64_ipi_wait(cpuset_t __volatile *cpus_watchset, cpuset_t cpus_mask) 334,336c353 < smp_tlb_flush_pte(va, ctx) < vaddr_t va; < int ctx; --- > smp_tlb_flush_pte(vaddr_t va, int ctx) 341c358 < #if defined(IPI_TLB_SHOOTDOWN) --- > #if 0 && defined(IPI_TLB_SHOOTDOWN) 354,355c371 < smp_tlb_flush_ctx(ctx) < int ctx; --- > smp_tlb_flush_ctx(int ctx) 360c376 < #if defined(IPI_TLB_SHOOTDOWN) --- > #if 0 && defined(IPI_TLB_SHOOTDOWN) 388,390c404 < sparc64_ipi_error(s, cpus_succeeded, cpus_expected) < const char *s; < cpuset_t cpus_succeeded, cpus_expected; --- > sparc64_ipi_error(const char *s, cpuset_t cpus_succeeded, cpuset_t cpus_expected) 400a415 > Index: arch/sparc64/sparc64/locore.s =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/locore.s,v retrieving revision 1.198 diff -r1.198 locore.s 61d60 < #undef PARANOID /* Extremely expensive consistency checks */ 63,66d61 < #ifdef DEBUG < #define TRAPTRACE /* Keep history of all traps (unsafe) */ < #endif < #undef FLTRACE /* Keep history of all page faults */ 92a88 > #include 436d431 < 438d432 < 482,485c476,477 < #ifdef DEBUG < #ifdef TRAPTRACE < #define TRACEME sethi %hi(1f), %g1; ba,pt %icc,traceit;\ < or %g1, %lo(1f), %g1; 1: --- > > #if KTR_COMPILE & KTR_TRAP 487,493d478 < #define TRACEWIN sethi %hi(9f), %l6; ba,pt %icc,traceitwin;\ < or %l6, %lo(9f), %l6; 9: < #endif /* 0 */ < #ifdef TRAPS_USE_IG < #define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_AG, %pstate;\ < sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9: < #else 495,510c480 < sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9: < #endif /* TRAPS_USE_IG */ < #define TRACERELOAD32 ba reload32; nop; < #define TRACERELOAD64 ba reload64; nop; < #define TRACEFLT TRACEME < #define VTRAP(type, label) \ < sethi %hi(label), %g1; ba,pt %icc,traceit;\ < or %g1, %lo(label), %g1; NOTREACHED; TA8 < #else /* TRAPTRACE */ < #define TRACEME < #define TRACEWIN TRACEME < #define TRACERELOAD32 < #define TRACERELOAD64 < #ifdef FLTRACE < #define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,traceit;\ < or %g1, %lo(1f), %g1; 1: --- > sethi %hi(9f), %g1; ba,pt %icc,ktr_trap_gen; or %g1, %lo(9f), %g1; 9: 512,536c482,485 < #define TRACEFLT TRACEME < #endif /* FLTRACE */ < #define VTRAP(type, label) \ < sethi %hi(DATA_START),%g1; rdpr %tt,%g2; or %g1,0x28,%g1; b label;\ < stx %g2,[%g1]; NOTREACHED; TA8 < #endif /* TRAPTRACE */ < #else /* DEBUG */ < #ifdef TRAPTRACE < #define TRACEME sethi %hi(1f), %g1; ba,pt %icc,traceit;\ < or %g1, %lo(1f), %g1; 1: < #if 0 < /* Can't use this 'cause we have no clean registers during a spill */ < #define TRACEWIN sethi %hi(9f), %l6; ba,pt %icc,traceitwin;\ < or %l6, %lo(9f), %l6; 9: < #endif /* 0 */ < #ifdef TRAPS_USE_IG < #define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_AG, %pstate;\ < sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9: < #else < #define TRACEWIN wrpr %g0, PSTATE_KERN|PSTATE_IG, %pstate;\ < sethi %hi(9f), %g1; ba,pt %icc,traceit; or %g1, %lo(9f), %g1; 9: < #endif /* TRAPS_USE_IG */ < #define TRACERELOAD32 ba reload32; nop; < #define TRACERELOAD64 ba reload64; nop; < #define TRACEFLT TRACEME --- > #define TRACEWIN > #endif > #define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,ktr_trap_gen;\ > or %g1, %lo(1f), %g1; 1: 538,550c487,491 < sethi %hi(label), %g1; ba,pt %icc,traceit;\ < or %g1, %lo(label), %g1; NOTREACHED; TA8 < #else /* TRAPTRACE */ < #define TRACEME < #define TRACEWIN TRACEME < #define TRACERELOAD32 < #define TRACERELOAD64 < #ifdef FLTRACE < #define TRACEFLT sethi %hi(1f), %g1; ba,pt %icc,traceit;\ < or %g1, %lo(1f), %g1; 1: < #else < #define TRACEFLT TRACEME < #endif /* FLTRACE */ --- > sethi %hi(label), %g1; ba,pt %icc,ktr_trap_gen;\ > or %g1, %lo(label), %g1; NOTREACHED; TA8 > #else > #define TRACEWIN > #define TRACEFLT 553,554c494,495 < #endif /* TRAPTRACE */ < #endif /* DEBUG */ --- > #endif > 601a543 > 777c719 < VTRAP(T_FP_IEEE_754, fp_exception) ! 021 = ieee 754 exception --- > VTRAP(T_FP_IEEE_754, fp_exception) ! 021 = ieee 754 exception 878c820 < TRACEFLT ! DEBUG --- > TRACEFLT 1034c976 < VTRAP(T_FP_IEEE_754, fp_exception) ! 021 = ieee 754 exception --- > VTRAP(T_FP_IEEE_754, fp_exception) ! 021 = ieee 754 exception 1121c1063 < TRACEFLT ! DEBUG --- > TRACEFLT 1457a1400 > 1461,1493d1403 < #define TRACEIT(tt,r3,r4,r2,r6,r7) \ < set trap_trace, r2; \ < lduw [r2+TRACEDIS], r4; \ < brnz,pn r4, 1f; \ < lduw [r2+TRACEPTR], r3; \ < rdpr %tl, r4; \ < cmp r4, 1; \ < sllx r4, 13, r4; \ < rdpr %pil, r6; \ < or r4, %g5, r4; \ < mov %g0, %g5; \ < andncc r3, (TRACESIZ-1), %g0; /* At end of buffer? */ \ < sllx r6, 9, r6; \ < or r6, r4, r4; \ < movnz %icc, %g0, r3; /* Wrap buffer if needed */ \ < rdpr %tstate, r6; \ < rdpr %tpc, r7; \ < sth r4, [r2+r3]; \ < inc 2, r3; \ < sth %g5, [r2+r3]; \ < inc 2, r3; \ < stw r6, [r2+r3]; \ < inc 4, r3; \ < stw %sp, [r2+r3]; \ < inc 4, r3; \ < stw r7, [r2+r3]; \ < inc 4, r3; \ < mov TLB_TAG_ACCESS, r7; \ < ldxa [r7] ASI_DMMU, r7; \ < stw r7, [r2+r3]; \ < inc 4, r3; \ < stw r3, [r2+TRACEPTR]; \ < 1: 1571,1627d1480 < traceitwin: < set trap_trace, %l2 < lduw [%l2+TRACEDIS], %l4 < brnz,pn %l4, 1f < nop < lduw [%l2+TRACEPTR], %l3 < rdpr %tl, %l4 < rdpr %tt, %l5 < sllx %l4, 13, %l4 < or %l4, %l5, %l4 < clr %l5 ! Don't load PID < andncc %l3, (TRACESIZ-1), %g0 < movnz %icc, %g0, %l3 ! Wrap? < < clr %l0 ! Don't load nsaved < sllx %l0, 9, %l1 < or %l1, %l4, %l4 < rdpr %tpc, %l7 < < sth %l4, [%l2+%l3] < inc 2, %l3 < sth %l5, [%l2+%l3] < inc 2, %l3 < stw %l0, [%l2+%l3] < inc 4, %l3 < stw %sp, [%l2+%l3] < inc 4, %l3 < stw %l7, [%l2+%l3] < inc 4, %l3 < stw %g0, [%l2+%l3] < inc 4, %l3 < stw %l3, [%l2+TRACEPTR] < 1: < jmpl %l6, %g0 < nop < reload64: < ldxa [%sp+BIAS+0x00]%asi, %l0 < ldxa [%sp+BIAS+0x08]%asi, %l1 < ldxa [%sp+BIAS+0x10]%asi, %l2 < ldxa [%sp+BIAS+0x18]%asi, %l3 < ldxa [%sp+BIAS+0x20]%asi, %l4 < ldxa [%sp+BIAS+0x28]%asi, %l5 < ldxa [%sp+BIAS+0x30]%asi, %l6 < ldxa [%sp+BIAS+0x38]%asi, %l7 < CLRTT < retry < reload32: < lda [%sp+0x00]%asi, %l0 < lda [%sp+0x04]%asi, %l1 < lda [%sp+0x08]%asi, %l2 < lda [%sp+0x0c]%asi, %l3 < lda [%sp+0x10]%asi, %l4 < lda [%sp+0x14]%asi, %l5 < lda [%sp+0x18]%asi, %l6 < lda [%sp+0x1c]%asi, %l7 < CLRTT < retry 1629a1483,1502 > #if KTR_COMPILE > .text > ktr_trap_gen: > CATR(KTR_TRAP, "TRAP: tl=%d tt=%p tstate=%p tpc=%p sp=%p", > %g2, %g3, %g4, 10, 11, 12) > rdpr %tl, %g3 > stx %g3, [%g2 + KTR_PARM1] > rdpr %tt, %g3 > stx %g3, [%g2 + KTR_PARM2] > rdpr %tstate, %g3 > stx %g3, [%g2 + KTR_PARM3] > rdpr %tpc, %g3 > stx %g3, [%g2 + KTR_PARM4] > stx %sp, [%g2 + KTR_PARM5] > 12: > jmp %g1 ! return to processing the trap > nop > #endif > > 2196a2070,2073 > #if 0 & KTR_COMPILE & KTR_TRAP > CATR(KTR_TRAP, "data_miss:", %g3, %g4, %g5, 10, 11, 12) > 12: > #endif 2320,2326d2196 < #ifdef DEBUG < sethi %hi(DATA_START), %g7 ! debug < ! stx %g0, [%g7] ! debug This is a real fault -- prevent another trap from watchdoging < set 0x10, %g4 ! debug < stb %g4, [%g7 + 0x20] ! debug < CHKPT(%g4,%g7,0x19) < #endif 2476c2346 < bne,a,pt %xcc, datafault ! Was not a spill -- handle it normally --- > bne,a,pt %xcc, datafault ! Was not a spill -- handle it normally 2483,2485c2353,2355 < btst TSTATE_PRIV, %g4 ! From user mode? < wrpr %g2, 0, %tl ! We need to load the fault type so we can < rdpr %tt, %g5 ! overwrite the lower trap and get it to the fault handler --- > btst TSTATE_PRIV, %g4 ! From user mode? > wrpr %g2, 0, %tl ! We need to load the fault type so we can > rdpr %tt, %g5 ! overwrite the lower trap and get it to the fault handler 2487,2488c2357,2358 < wrpr %g5, 0, %tt ! Copy over trap type for the fault handler < and %g4, CWP, %g5 ! find %cwp from trap --- > wrpr %g5, 0, %tt ! Copy over trap type for the fault handler > and %g4, CWP, %g5 ! find %cwp from trap 2490,2491c2360,2361 < be,a,pt %xcc, datafault ! Let's do a regular datafault. When we try a save in datafault we'll < wrpr %g5, 0, %cwp ! return here and write out all dirty windows. --- > be,a,pt %xcc, datafault ! Let's do a regular datafault. When we try a save in datafault we'll > wrpr %g5, 0, %cwp ! return here and write out all dirty windows. 2493c2363 < bne,pt %xcc, 3f ! Let's do a regular datafault. When we try a save in datafault we'll --- > bne,pt %xcc, 3f ! Let's do a regular datafault. When we try a save in datafault we'll 2495c2365 < wrpr %g5, 0, %cwp ! return here and write out all dirty windows. --- > wrpr %g5, 0, %cwp ! return here and write out all dirty windows. 3164d3033 < 3223c3092 < 1: --- > 1: 3259d3127 < 3284c3152 < rdpr %tt, %o1 ! Find out what caused this trap --- > rdpr %tt, %o1 ! Find out what caused this trap 3288c3156 < rdpr %tpc, %o2 ! sync virt addr; must be read first --- > rdpr %tpc, %o2 ! sync virt addr; must be read first 3292c3160 < rd %y, %g7 ! save y --- > rd %y, %g7 ! save y 3296c3164 < sth %o1, [%sp + CC64FSZ + STKB + TF_TT]! debug --- > sth %o1, [%sp + CC64FSZ + STKB + TF_TT] ! debug 3535a3404,3405 > flushw ! XXXPETR > 4020,4035c3890,3897 < #if NOT_DEBUG < STACKFRAME(-CC64FSZ) ! Get a clean register window < mov %g1, %o2 < mov %g2, %o3 < < ldxa [%g0] ASI_MID_REG, %o1 < srax %o1, 17, %o1 ! Isolate UPAID from CPU reg < and %o1, 0x1f, %o1 < < LOAD_ASCIZ(%o0, "cpu%d: interrupt_vector: ASI_IRSR %lx ASI_IRDR(0x40) %lx\r\n") < GLOBTOLOC < call prom_printf < clr %g4 < LOCTOGLOB < restore < nop --- > #if KTR_COMPILE & KTR_INTR > CATR(KTR_TRAP, "interrupt_vector: tl %d ASI_IRSR %p ASI_IRDR %p", > %g3, %g5, %g6, 10, 11, 12) > rdpr %tl, %g5 > stx %g5, [%g3 + KTR_PARM1] > stx %g1, [%g3 + KTR_PARM2] > stx %g2, [%g3 + KTR_PARM3] > 12: 4051c3913,3916 < jmpl %g1, %o7 --- > brz,pn %g1, ret_from_intr_vector > nop > > jmpl %g1, %g0 4053a3919,3921 > 10: ta 1 > nop > 4058c3926 < #if DEBUG --- > #if NOT_DEBUG 4101c3969 < #ifdef DEBUG --- > #ifdef NOT_DEBUG 4128c3996 < #ifdef DIAGNOSTIC --- > #ifdef NOT_DIAGNOSTIC 4144c4012 < #ifdef DEBUG --- > #ifdef NOT_DEBUG 4170c4038,4048 < CLRTT --- > #if KTR_COMPILE & KTR_INTR > CATR(KTR_TRAP, "ret_from_intr_vector: tl %d, tstate %p, tpc %p", > %g3, %g4, %g5, 10, 11, 12) > rdpr %tl, %g5 > stx %g5, [%g3 + KTR_PARM1] > rdpr %tstate, %g5 > stx %g5, [%g3 + KTR_PARM2] > rdpr %tpc, %g5 > stx %g5, [%g3 + KTR_PARM3] > 12: > #endif 4175c4053 < #ifdef DEBUG --- > #ifdef NOT_DEBUG 4181a4060 > #if 0 4191a4071 > #endif 4203a4084,4088 > #if 0 & KTR_COMPILE & KTR_PMAP > CATR(KTR_TRAP, "sparc64_ipi_flush_pte:", > %g1, %g3, %g4, 10, 11, 12) > 12: > #endif 4215a4101,4105 > #if KTR_COMPILE & KTR_PMAP > CATR(KTR_TRAP, "sparc64_ipi_flush_ctx:", > %g1, %g3, %g4, 10, 11, 12) > 12: > #endif 4228,4230c4118,4128 < rdpr %pstate, %g3 < andn %g3, PSTATE_IE, %g2 ! disable interrupts < wrpr %g2, 0, %pstate --- > ! rdpr %pstate, %g3 > ! andn %g3, PSTATE_IE, %g2 ! disable interrupts > ! wrpr %g2, 0, %pstate > #if 0 & KTR_COMPILE & KTR_PMAP > CATR(KTR_TRAP, "sparc64_ipi_flush_all: %p %p", > %g1, %g4, %g5, 10, 11, 12) > stx %g3, [%g1 + KTR_PARM1] > stx %g2, [%g1 + KTR_PARM2] > 12: > #endif > 4243c4141 < --- > 4268c4166 < sethi %hi(KERNBASE), %g4 --- > ! sethi %hi(KERNBASE), %g1 4270,4271c4168,4169 < flush %g4 < wrpr %g3, %pstate --- > ! flush %g1 > ! wrpr %g3, %pstate 4663,4681d4560 < #ifdef NOTDEF_DEBUG < mov %i6, %o1 < save %sp, -CC64FSZ, %sp < set 1f, %o0 < mov %i1, %o1 < ldx [%fp + CC64FSZ + STKB + TF_PC], %o3 < ldx [%fp + CC64FSZ + STKB + TF_NPC], %o4 < GLOBTOLOC < call printf < mov %i6, %o2 < LOCTOGLOB < restore < .data < 1: .asciz "rft[%x,%x,%p,%p]" < 3: .asciz "return_from_trap: fp=%x sp=%x pc=%x\n" < _ALIGN < .text < 2: < #endif 4683,4710c4562,4572 < #ifdef NOTDEF_DEBUG < ldx [%sp + CC64FSZ + STKB + TF_TSTATE], %g2 < set TSTATE_AG, %g3 < set 4f, %g4 < and %g2, %g3, %g3 < clr %o1 < movrnz %g3, %g4, %o1 < set TSTATE_MG, %g3 < set 3f, %g4 < and %g2, %g3, %g3 < movrnz %g3, %g4, %o1 < set TSTATE_IG, %g3 < set 5f, %g4 < and %g2, %g3, %g3 < movrnz %g3, %g4, %o1 < brz,pt %o1, 2f < set 1f, %o0 < call printf < nop < ta 1; nop < .data < 1: .asciz "Returning to trap from %s globals\n" < 3: .asciz "MMU" < 4: .asciz "Altermate" < 5: .asciz "Interrupt" < _ALIGN < .text < 2: --- > #if KTR_COMPILE & KTR_TRAP > CATR(KTR_TRAP, "rft: sp=%p pc=%p npc=%p tstate=%p", > %g2, %g3, %g4, 10, 11, 12) > stx %i6, [%g2 + KTR_PARM1] > ldx [%sp + CC64FSZ + STKB + TF_PC], %g3 > stx %g3, [%g2 + KTR_PARM2] > ldx [%sp + CC64FSZ + STKB + TF_NPC], %g3 > stx %g3, [%g2 + KTR_PARM3] > ldx [%sp + CC64FSZ + STKB + TF_TSTATE], %g3 > stx %g3, [%g2 + KTR_PARM4] > 12: 4711a4574 > 6021a5885 > wrpr %g0, 0, %tl 6306a6171,6173 > sethi %hi(CPCB), %l6 > LDPTR [%l7 + %lo(CURLWP)], %l4 > LDPTR [%l6 + %lo(CPCB)], %l5 6412,6413c6279,6280 < STACKFRAME(-CC64FSZ) ! Flush register windows < flushw --- > STACKFRAME(-CC64FSZ) > flushw ! Flush register windows 7743c7610 < * %l5 = oldpsr (excluding ipl bits) --- > * %l5 = cpcb 7767,7778c7634,7637 < #ifdef SCHED_DEBUG < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < call printf < nop < LOCTOGLOB < restore < .data < 1: .asciz "switchexit()\r\n" < _ALIGN < .text --- > #if KTR_COMPILE & KTR_TRAP > CATR(KTR_TRAP, "cpu_exit:", > %g2, %g3, %g4, 10, 11, 12) > 12: 7882a7742,7757 > ENTRY_NOPROFILE(idle_switch) > sethi %hi(IDLE_U), %l1 > LDPTR [%l1 + %lo(IDLE_U)], %l1 > sethi %hi(CPCB), %l6 > > STPTR %l1, [%l6 + %lo(CPCB)] ! cpcb = curcpu()->ci_idle_u > set USPACE - CC64FSZ - 80, %o0 ! set new %sp > LDPTR [%l6 + %lo(CPCB)], %l5 > add %l1, %o0, %o0 > #ifdef _LP64 > sub %o0, BIAS, %sp > #else > mov %o0, %sp > #endif > clr %l4 > 7887a7763,7770 > > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "idle: pcb %p, idle_u %p", > %g2, %g3, %g4, 10, 11, 12) > stx %l5, [%g2 + KTR_PARM1] > stx %l1, [%g2 + KTR_PARM2] > 12: > #endif 7891,7907d7773 < #ifdef NOTDEF_DEBUG < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set idlemsg, %o0 < mov %g1, %o1 < mov %g2, %o2 < mov %g3, %o3 < call _C_LABEL(prom_printf) < mov %g4, %o4 < set idlemsg1, %o0 < mov %l5, %o1 < mov %l6, %o2 < call _C_LABEL(prom_printf) < mov %l7, %o3 < LOCTOGLOB < restore < #endif 7951,7952d7816 < idlemsg: .asciz "idle %x %x %x %x" < idlemsg1: .asciz " %x %x %x\r\n" 7992,8006d7855 < #ifdef DEBUG < set swdebug, %o1 < ld [%o1], %o1 < brz,pt %o1, 2f < set 1f, %o0 < call printf < nop < .data < 1: .asciz "s" < _ALIGN < .globl swdebug < swdebug: .word 0 < .text < 2: < #endif 8012,8017c7861,7862 < flushw ! We don't have anything else to run, so why not flush < #ifdef NOTDEF_DEBUG < save %sp, -CC64FSZ, %sp < flushw < restore < #endif --- > flushw ! XXX We don't have anything else to run, so why not flush > 8022a7868 > 8024d7869 < stx %o7, [%l5 + PCB_PC] ! cpcb->pcb_pc = pc; 8026c7871 < sth %o1, [%l5 + PCB_PSTATE] ! cpcb->pcb_pstate = oldpstate; --- > sth %o1, [%l5 + PCB_PSTATE] ! cpcb->pcb_pstate = oldpstate; 8029a7875,7890 > stx %i7, [%l5 + PCB_PC] ! cpcb->pcb_pc = pc; > stx %i6, [%l5 + PCB_SP] > > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: %p", > %g2, %g3, %g1, 10, 11, 12) > stx %l4, [%g2 + KTR_PARM1] > 12: > #endif > > #if defined(MULTIPROCESSOR) > ld [%l2 + %lo(_C_LABEL(sched_whichqs))], %o3 > brz,pt %o3, idle_switch > nop > #endif > 8107,8108c7968,7969 < * %l3 = p < * %l4 = lastproc --- > * %l3 = l > * %l4 = lastlwp(proc) 8130c7991 < * Committed to running process p. --- > * Committed to running lwp l. 8135c7996 < * p->p_cpu = curcpu(); --- > * l->l_cpu = curcpu(); 8145,8146c8006,8007 < LDPTR [%l3 + L_ADDR], %l1 ! newpcb = p->p_addr; < STPTR %g0, [%l3 + L_BACK] ! p->p_back = NULL; --- > LDPTR [%l3 + L_ADDR], %l1 ! newpcb = l->l_addr; > STPTR %g0, [%l3 + L_BACK] ! l->l_back = NULL; 8154c8015,8023 < STPTR %l4, [%l7 + %lo(CURLWP)] ! restore old proc so we can save it --- > STPTR %l4, [%l7 + %lo(CURLWP)] ! restore old lwp so we can save it > > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: %p->%p", > %g2, %g3, %g1, 10, 11, 12) > stx %l4, [%g2 + KTR_PARM1] > stx %l3, [%g2 + KTR_PARM2] > 12: > #endif 8162,8163c8031,8032 < * Not the old process. Save the old process, if any; < * then load p. --- > * Not the old lwp. Save the old lwp, if any; > * then load l. 8165,8183d8033 < #ifdef SCHED_DEBUG < mov %l4, %g1 < mov %l3, %g2 < save %sp, -CC64FSZ, %sp < set 1f, %o0 < mov %g1, %o1 < ld [%o1+P_PID], %o2 < mov %g2, %o3 < call printf < ld [%o3+P_PID], %o4 < ba 2f < restore < .data < 1: .asciz "cpu_switch: %x(%d)->%x(%d)\r\n" < _ALIGN < .text < Debugger(); < 2: < #endif 8191c8041 < stx %i7, [%l5 + PCB_PC] ! Save rpc --- > stx %i7, [%l5 + PCB_PC] ! Save pc 8194a8045,8051 > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: (wb1) saved pc=%p, fp=%p", > %g2, %g3, %g1, 10, 11, 12) > stx %i7, [%g2 + KTR_PARM1] > stx %i6, [%g2 + KTR_PARM2] > 12: > #endif 8204,8215c8061,8066 < #ifdef SCHED_DEBUG < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < call printf < nop < LOCTOGLOB < restore < .data < 1: .asciz "cpu_switch: loading the new process:\r\n" < _ALIGN < .text --- > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: (Lsw_load) %p, pcb %p", > %g2, %g3, %g1, 10, 11, 12) > stx %l3, [%g2 + KTR_PARM1] > stx %l1, [%g2 + KTR_PARM2] > 12: 8218,8219c8069,8070 < STPTR %l3, [%l7 + %lo(CURLWP)] ! curlwp = p; < STPTR %l1, [%l6 + %lo(CPCB)] ! cpcb = newpcb; --- > STPTR %l3, [%l7 + %lo(CURLWP)] ! curlwp = l; > STPTR %l1, [%l6 + %lo(CPCB)] ! cpcb = newpcb; 8221,8241d8071 < #ifdef SCHED_DEBUG < ldx [%l1 + PCB_SP], %o0 < btst 1, %o0 < add %o0, BIAS, %o1 < movnz %icc, %o1, %o0 < brnz,pt %o0, 2f < ldx [%o0], %o0 ! Force a fault if needed < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < call printf < nop < LOCTOGLOB < restore < ta 1 < .data < 1: .asciz "cpu_switch: NULL %sp\r\n" < _ALIGN < .text < 2: < #endif 8252,8272c8082,8087 < #ifdef DEBUG < wrpr %g0, 4, %tl ! DEBUG -- force watchdog < flushw ! DEBUG < wrpr %g0, 0, %tl ! DEBUG < /* load window */ < ! restore ! The logic is just too complicated to handle here. Let the traps deal with the problem < ! flushw ! DEBUG < #endif < #ifdef SCHED_DEBUG < mov %fp, %i1 < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < call printf < mov %i1, %o1 < LOCTOGLOB < restore < .data < 1: .asciz "cpu_switch: setup new process stack regs at %08x\r\n" < _ALIGN < .text --- > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: new lwp pc=%p, sp=%p", > %g2, %g3, %g1, 10, 11, 12) > stx %i7, [%g2 + KTR_PARM1] > stx %i6, [%g2 + KTR_PARM2] > 12: 8273a8089 > 8287,8288c8103,8104 < LDPTR [%l3 + L_PROC], %l4 ! now %l4 points to p < LDPTR [%l4 + P_VMSPACE], %o3 ! vm = p->p_vmspace; --- > LDPTR [%l3 + L_PROC], %l4 ! now %l4 points to p > LDPTR [%l4 + P_VMSPACE], %o3 ! vm = p->p_vmspace; 8298c8114 < --- > 8303,8315c8119,8123 < #ifdef SCHED_DEBUG < mov %o0, %g1 < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < call printf < mov %g1, %o1 < LOCTOGLOB < restore < .data < 1: .asciz "cpu_switch: got new ctx %d in new process\r\n" < _ALIGN < .text --- > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: new ctx %d", > %g2, %g3, %g1, 10, 11, 12) > stx %o0, [%g2 + KTR_PARM1] > 12: 8316a8125 > 8327,8386d8135 < #ifdef SCHED_DEBUG < mov %o0, %g1 < mov %i7, %g1 < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < mov %g1, %o2 < call printf < mov %g2, %o1 < LOCTOGLOB < restore < .data < 1: .asciz "cpu_switch: in new process pc=%08x ctx %d\r\n" < _ALIGN < .text < #endif < #ifdef TRAPTRACE < set trap_trace, %o2 < lduw [%o2+TRACEDIS], %o4 < brnz,pn %o4, 1f < nop < lduw [%o2+TRACEPTR], %o3 < rdpr %tl, %o4 < mov 4, %o5 < set CURLWP, %o0 < sllx %o4, 13, %o4 < LDPTR [%o0], %o0 < ! clr %o0 ! DISABLE PID < or %o4, %o5, %o4 < mov %g0, %o5 < brz,pn %o0, 2f < andncc %o3, (TRACESIZ-1), %g0 < ! ldsw [%o0+P_PID], %o5 ! Load PID < 2: < movnz %icc, %g0, %o3 ! Wrap if needed < < set CPCB, %o0 ! Load up nsaved < LDPTR [%o0], %o0 < ldub [%o0 + PCB_NSAVED], %o0 < sllx %o0, 9, %o1 < or %o1, %o4, %o4 < < sth %o4, [%o2+%o3] < inc 2, %o3 < sth %o5, [%o2+%o3] < inc 2, %o3 < stw %o0, [%o2+%o3] < inc 4, %o3 < stw %sp, [%o2+%o3] < inc 4, %o3 < stw %o7, [%o2+%o3] < inc 4, %o3 < mov TLB_TAG_ACCESS, %o4 < ldxa [%o4] ASI_DMMU, %o4 < stw %o4, [%o2+%o3] < inc 4, %o3 < stw %o3, [%o2+TRACEPTR] < 1: < #endif < 8400a8150,8155 > #if KTR_COMPILE & KTR_PROC > CATR(KTR_TRAP, "cpu_switch: ras pc=%p", > %g2, %g3, %g1, 10, 11, 12) > stx %o0, [%g2 + KTR_PARM1] > 12: > #endif 8409,8441d8163 < #ifdef SCHED_DEBUG < mov %l0, %o0 ! XXXXX < save %sp, -CC64FSZ, %sp < GLOBTOLOC < set 1f, %o0 < mov %i0, %o2 < set CURLWP, %o3 < LDPTR [%o3], %o3 < ld [%o3 + P_VMSPACE], %o3 < call printf < mov %i7, %o1 < #ifdef DEBUG < set swtchdelay, %o0 < call delay < ld [%o0], %o0 < set pmapdebug, %o0 < ld [%o0], %o0 < tst %o0 < tnz %icc, 1; nop ! Call debugger if we're in pmapdebug < #endif < LOCTOGLOB < ba 2f ! Skip debugger < restore < .data < 1: .asciz "cpu_switch: vectoring to pc=%08x thru %08x vmspace=%p\r\n" < _ALIGN < .globl swtchdelay < swtchdelay: < .word 1000 < .text < Debugger(); < 2: < #endif Index: arch/sparc64/sparc64/pmap.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/pmap.c,v retrieving revision 1.156 diff -r1.156 pmap.c 1325d1324 < cpus->ci_cpcb = (struct pcb *)u0[0]; /* Need better source */ 1332d1330 < cpus->ci_initstack = (void *)u0[1]; 1334d1331 < cpus->ci_eintstack = (void *)EINTSTACK; 1335a1333,1344 > #if 0 > cpus->ci_cpcb = (struct pcb *)u0[0]; /* Need better source */ > #endif > #if 1 > cpus->ci_cpcb = cpus->ci_idle_u; > proc0paddr = (struct pcb *)cpus->ci_idle_u; > cpus->ci_initstack = (void *)((vaddr_t)cpus->ci_idle_u + 2 * PAGE_SIZE); > /* (void *)u0[1]; */ > #endif > cpus->ci_initstack = (void *)((vaddr_t)cpus->ci_idle_u + 2 * PAGE_SIZE); > /* (void *)u0[1]; */ > cpus->ci_eintstack = (void *)EINTSTACK; 2283a2293,2297 > } else if (pm == pmap_kernel() && va >= INTSTACK && va < (INTSTACK + 4*USPACE)) { > /* XXX */ > pa = (paddr_t)(curcpu()->ci_paddr - INTSTACK + va); > DPRINTF(PDB_EXTRACT, ("pmap_extract: va=%lx pa=%llx\n", > (u_long)va, (unsigned long long)pa)); Index: arch/sparc64/sparc64/trap.c =================================================================== RCS file: /cvsroot/src/sys/arch/sparc64/sparc64/trap.c,v retrieving revision 1.116 diff -r1.116 trap.c 62a63 > #include "opt_ktr.h" 85a87 > #include 124d125 < int trapstats = 0; 382,383c383,384 < static __inline void share_fpu __P((struct lwp *, struct trapframe64 *)); < static __inline void userret __P((struct lwp *, int, u_quad_t)); --- > static __inline void share_fpu (struct lwp *, struct trapframe64 *); > static __inline void userret (struct lwp *, int, u_quad_t); 385,394c386,395 < void trap __P((struct trapframe64 *tf, unsigned type, vaddr_t pc, long tstate)); < void data_access_fault __P((struct trapframe64 *tf, unsigned type, vaddr_t pc, < vaddr_t va, vaddr_t sfva, u_long sfsr)); < void data_access_error __P((struct trapframe64 *tf, unsigned type, < vaddr_t afva, u_long afsr, vaddr_t sfva, u_long sfsr)); < void text_access_fault __P((struct trapframe64 *tf, unsigned type, < vaddr_t pc, u_long sfsr)); < void text_access_error __P((struct trapframe64 *tf, unsigned type, < vaddr_t pc, u_long sfsr, vaddr_t afva, u_long afsr)); < void syscall __P((struct trapframe64 *, register_t code, register_t pc)); --- > void trap (struct trapframe64 *tf, unsigned type, vaddr_t pc, long tstate); > void data_access_fault (struct trapframe64 *tf, unsigned type, vaddr_t pc, > vaddr_t va, vaddr_t sfva, u_long sfsr); > void data_access_error (struct trapframe64 *tf, unsigned type, > vaddr_t afva, u_long afsr, vaddr_t sfva, u_long sfsr); > void text_access_fault (struct trapframe64 *tf, unsigned type, > vaddr_t pc, u_long sfsr); > void text_access_error (struct trapframe64 *tf, unsigned type, > vaddr_t pc, u_long sfsr, vaddr_t afva, u_long afsr); > void syscall (struct trapframe64 *, register_t code, register_t pc); 397c398 < void print_trapframe __P((struct trapframe64 *)); --- > void print_trapframe (struct trapframe64 *); 399,400c400 < print_trapframe(tf) < struct trapframe64 *tf; --- > print_trapframe(struct trapframe64 *tf) 440,443c440 < userret(l, pc, oticks) < struct lwp *l; < int pc; < u_quad_t oticks; --- > userret(struct lwp *l, int pc, u_quad_t oticks) 475,477c472 < share_fpu(l, tf) < struct lwp *l; < struct trapframe64 *tf; --- > share_fpu(struct lwp *l, struct trapframe64 *tf) 483a479,480 > int fpdis_traps = 0; > 489,493c486 < trap(tf, type, pc, tstate) < struct trapframe64 *tf; < unsigned int type; < vaddr_t pc; < long tstate; --- > trap(struct trapframe64 *tf, unsigned int type, vaddr_t pc, long tstate) 507a501,506 > if (type == T_FPDISABLED) > fpdis_traps++; > > CTR5(KTR_TRAP, "trap: tf %p, type %x, pc %p, tstate %x, tf_pc %p", > tf, type, pc, tstate, tf->tf_pc); > 631a631,633 > #if defined(MULTIPROCESSOR) > extern int ipi_ignore; > #endif 638,639c640,641 < printf("trap type 0x%x: pc=%lx", < type, pc); --- > printf("trap type 0x%x: cpu %ld, pc=%lx", > type, CPU_UPAID, pc); 643a646,648 > #if defined(MULTIPROCESSOR) > ipi_ignore = 1; > #endif 952,953c957 < rwindow_save(l) < struct lwp *l; --- > rwindow_save(struct lwp *l) 1045,1046c1049 < kill_user_windows(l) < struct lwp *l; --- > kill_user_windows(struct lwp *l) 1058,1064c1061,1062 < data_access_fault(tf, type, pc, addr, sfva, sfsr) < struct trapframe64 *tf; < unsigned type; < vaddr_t pc; < vaddr_t addr; < vaddr_t sfva; < u_long sfsr; --- > data_access_fault(struct trapframe64 *tf, unsigned type, vaddr_t pc, > vaddr_t addr, vaddr_t sfva, u_long sfsr) 1079a1078,1080 > CTR4(KTR_TRAP, "data_access_fault: tf %p, type %x, pc %p, addr %p", > tf, type, pc, addr); > 1236d1236 < 1240,1241c1240 < printf("data fault: pc=%lx addr=%lx\n", < pc, addr); --- > printf("data fault: pc=%lx addr=%lx\n", pc, addr); 1301c1300 < extern void *return_from_trap __P((void)); --- > extern void *return_from_trap (void); 1318,1324c1317,1318 < data_access_error(tf, type, afva, afsr, sfva, sfsr) < struct trapframe64 *tf; < unsigned type; < vaddr_t sfva; < u_long sfsr; < vaddr_t afva; < u_long afsr; --- > data_access_error(struct trapframe64 *tf, unsigned type, vaddr_t sfva, > u_long sfsr, vaddr_t afva, u_long afsr) 1481,1485c1475 < text_access_fault(tf, type, pc, sfsr) < unsigned type; < vaddr_t pc; < struct trapframe64 *tf; < u_long sfsr; --- > text_access_fault(struct trapframe64 *tf, unsigned type, vaddr_t pc, u_long sfsr) 1496a1487,1490 > tstate = tf->tf_tstate; > CTR5(KTR_TRAP, "text_access_fault: tf %p, type %x, pc %p, tstate %x, tf_pc %p", > tf, type, pc, tstate, tf->tf_pc); > 1498a1493,1494 > __asm("ta 1; nop" : :); > #if 0 1501a1498 > #endif 1526d1522 < tstate = tf->tf_tstate; 1621,1627c1617,1618 < text_access_error(tf, type, pc, sfsr, afva, afsr) < struct trapframe64 *tf; < unsigned type; < vaddr_t pc; < u_long sfsr; < vaddr_t afva; < u_long afsr; --- > text_access_error(struct trapframe64 *tf, unsigned type, vaddr_t pc, > u_long sfsr, vaddr_t afva, u_long afsr) 1830,1833c1821 < syscall(tf, code, pc) < struct trapframe64 *tf; < register_t code; < register_t pc; --- > syscall(struct trapframe64 *tf, register_t code, register_t pc) 2156,2157c2144 < child_return(arg) < void *arg; --- > child_return(void *arg) 2182,2183c2169 < startlwp(arg) < void *arg; --- > startlwp(void *arg) 2207a2194,2211 > > void cpu_preswitch(struct lwp *l); > void cpu_preswitch(struct lwp *l) > { > if (fplwp != NULL && fplwp != l) { > printf("cpu_preswitch: fplwp %p, l %p\n", fplwp, l); > return; > } > > if (!fplwp) > return; > > if (l->l_md.md_fpstate) { > savefpstate(l->l_md.md_fpstate); > fplwp = NULL; > } > > } Index: conf/files =================================================================== RCS file: /cvsroot/src/sys/conf/files,v retrieving revision 1.679 diff -r1.679 files 21a22,24 > defflag KTR > defparam opt_ktr.h KTR_COMPILE > defflag opt_ktr.h KTR_VERBOSE 1162a1166 > file kern/kern_ktr.c ktr Index: ddb/db_command.c =================================================================== RCS file: /cvsroot/src/sys/ddb/db_command.c,v retrieving revision 1.76 diff -r1.76 db_command.c 38a39 > #include "opt_ktr.h" 152a154,156 > #if defined(KTR) > { "ktr", db_show_ktr, 0, NULL }, > #endif Index: ddb/db_interface.h =================================================================== RCS file: /cvsroot/src/sys/ddb/db_interface.h,v retrieving revision 1.12 diff -r1.12 db_interface.h 71a72,74 > /* kern/kern_ktr.c */ > void db_show_ktr(db_expr_t, int, db_expr_t, char *); > Index: dev/sun/kbd.c =================================================================== RCS file: /cvsroot/src/sys/dev/sun/kbd.c,v retrieving revision 1.40 diff -r1.40 kbd.c 76,77c76 < < #include "locators.h" --- > #include 967a967 > #if 0 969a970 > #endif 1006a1008,1025 > /* struct kbd_softc *k = v; */ > > #if 0 > printf("wssunkbd_ioctl: cmd _IO%s%s('%c', %lu)\n", > (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", > (char)IOCGROUP(cmd), cmd & 0xff); > #endif > > switch (cmd) { > case WSKBDIO_GTYPE: > *((u_int *)data) = WSKBD_TYPE_SUN5; > return 0; > > case WSKBDIO_GETLEDS: > *(int *) data = 0; > return 0; > } > 1016c1035,1046 < /* struct kbd_sun_softc *k = v; */ --- > #if 0 > struct kbd_sun_softc *k = v; > struct kbd_state *ks = &k->k_kbd.k_state; > > int zscngetc(dev_t); > int code; > > code = zscngetc(0); > > *type = KEY_UP(code) ? WSCONS_EVENT_KEY_UP : WSCONS_EVENT_KEY_DOWN; > *data = KEY_CODE(code); > #endif 1064c1094 < k->k_wsenabled = 0; --- > k->k_wsenabled = 0 /* XXX don't know the knob 0 */; 1065a1096,1098 > > if (k->k_wskbd != NULL && a.console) > wssunkbd_enable(k, 1); /* in wscons the console is always */ Index: dev/sun/kbd_zs.c =================================================================== RCS file: /cvsroot/src/sys/dev/sun/kbd_zs.c,v retrieving revision 1.16 diff -r1.16 kbd_zs.c 106a107,110 > #if NWSKBD > 0 > void kbd_wskbd_attach(struct kbd_softc *k, int isconsole); > #endif > 190a195,199 > > #if NWSKBD > 0 > kbd_wskbd_attach(&k->k_kbd, k->k_kbd.k_isconsole); > k->k_kbd.k_wsenabled = 1; > #endif Index: kern/kern_synch.c =================================================================== RCS file: /cvsroot/src/sys/kern/kern_synch.c,v retrieving revision 1.144 diff -r1.144 kern_synch.c 84a85 > #include "opt_ktr.h" 99a101 > #include 616a619,626 > if (l->l_savp == NULL) { > #if 0 > printf("sa_awaken: no l_savp, l %p, flags %x\n", > l, l->l_flag); > #endif > return; > } > 934a945,948 > #if defined (MULTIPROCESSOR) > extern void cpu_preswitch(struct lwp *); > cpu_preswitch(l); > #endif 936a951,953 > #if defined(MULTIPROCESSOR) > printf("mi_switch: cpu_switchto %p %p\n", l, newl); > #endif Index: kern/subr_autoconf.c =================================================================== RCS file: /cvsroot/src/sys/kern/subr_autoconf.c,v retrieving revision 1.89 diff -r1.89 subr_autoconf.c 1251a1252,1264 > #ifdef DEBUG > void device_tree_dump(void); > void > device_tree_dump() > { > struct device *d; > > for (d = TAILQ_FIRST(&alldevs); d != NULL; d = TAILQ_NEXT(d, dv_list)) { > printf("%s: self %p, parent %p\n", > d->dv_xname, d, d->dv_parent); > } > } > #endif Index: uvm/uvm_page.c =================================================================== RCS file: /cvsroot/src/sys/uvm/uvm_page.c,v retrieving revision 1.98 diff -r1.98 uvm_page.c 1612a1613,1629 > > void uvm_dump_physmem(void); > void > uvm_dump_physmem() > { > int i; > > printf("physmem: nsegs %d\n", vm_nphysseg); > > for (i = 0; i < vm_nphysseg; i++) { > printf("#%2d: %lx-%lx, %lx-%lx pgs %p last %p\n", > i, > ptoa(vm_physmem[i].start), ptoa(vm_physmem[i].end), > ptoa(vm_physmem[i].avail_start), ptoa(vm_physmem[i].avail_end), > vm_physmem[i].pgs, vm_physmem[i].lastpg); > } > }